An electronic circuit is chemically and physically integrated into a substrate such as a silicon wafer by patterning regions in the substrate, and by patterning layers on the substrate. These regions and layers can be conductive, for conductor and resistor fabrication, or insulative, for insulator and capacitor fabrication. They can also be of differing conductivity types, for example p-type and n-type, which is essential for transistor and diode fabrication. Degrees of resistance, capacitance, and conductivity are controllable, as are the physical dimensions and locations of the patterned regions and layers, making circuit integration possible. Fabrication can be quite complex and time consuming, and therefore expensive. It is thus a continuing goal of those in the semiconductor fabrication business to reduce fabrication times and costs of such devices in order to increase profits. Any simplified processing step or combination of processes at a single step becomes a competitive advantage.
A situation where a process simplification is desirable is in the formation of structures in polycrystalline silicon having differing conductivity types. Polycrystalline silicon is resistive in nature, but is made less resistive when doped with an element having less or more than four valence electrons (depending on the conductivity type), or when layered with conductive silicide. In this disclosure, "n-type" denotes silicon that has been doped with atoms having more than four valence electrons (group V or higher), such as arsenic or phosphorus, which introduce negatively charged majority carriers into the silicon, and "p-type" denotes silicon doped with atoms having less than four valence electrons (group III or lower) , such as boron, which introduce positively charged majority carriers. The majority charge carrier type is also referred to as conductivity type. "Poly" and "polysilicon" denote polycrystalline silicon. By photomasking, geometries on the order of a micron or less are obtainable for device elements in the IC.
As devices are scaled down below 0.5 microns (.mu.m), some of the conventional technology becomes less useful. In particular, the gate structure of a conventional memory device, for example, is a concern below 0.35 .mu.m. N+ polysilicon is currently the most widely used material for both n- and p-channel device gates, but when applied to sub-halfmicron devices it can contribute to serious short channel effects found in buried p-channel devices. One method to limit these short channel effects is to use a halo implant, which has the disadvantage of limiting the minimum channel length attainable at approximately the sub-halfmicron boundary. A method with fewer shortcomings is to use dual polysilicon gate materials, for example n+ poly for the n-channel gates and p+ poly for the p-channel gates.
FIGS. 1a-1c show a conventional process for doping a polycrystalline silicon layer with two different materials, for example boron to produce p-type areas and phosphorous to produce n-type areas. In FIG. 1A, a substrate 10 having doped wells of p-type 12 and n-type 14 material is layered with an insulation layer 16, for example oxide to form a gate oxide layer, and an undoped poly layer 18. A photoresist layer 20 is patterned onto the surface over the p-wells to prevent doping, while areas of poly over the n-wells are left exposed. The exposed poly is doped with the boron to form p-type poly 18A over the n-wells 14, the photoresist 20 is stripped, and a second photoresist layer 22 is masked onto the poly areas over the p-type poly as shown in FIG. 1B. The exposed poly is doped with phosphorous to form n-type poly 18B and the photoresist 22 is stripped to form the structure of FIG. 1C. Wafer processing continues according to means known in the art.
The formation of this structure conventionally requires two mask steps. A process which formed the structure with a single mask step would be desirable, as additional mask steps are undesirable. For example, misalignment can easily occur, especially as device features decrease in size to below 0.5 .mu.m.